Gerard R. Williams, III Inventions, Patents and Patent Applications (2022)

Gerard R. Williams, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hashing with Soft Memory Folding

    Publication number: 20220342806

    Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

    Type: Application

    Filed: November 4, 2021

    Publication date: October 27, 2022

    Inventors: Steven Fishwick, Jeffry E. Gonion, Per H. Hammarlund, Eran Tamari, Lior Zimet, Gerard R. Williams, III

  • Systems and Methods for Coherent Power Management

    Publication number: 20220137692

    Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g., with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

    Type: Application

    Filed: November 17, 2021

    Publication date: May 5, 2022

    Inventors: Joseph T. DiBene, II, Inder M. Sodhi, Keith Cox, Gerard R. Williams, III

  • Systems and methods for coherent power management

    Patent number: 11204636

    Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

    Type: Grant

    Filed: July 23, 2019

    Date of Patent: December 21, 2021

    Assignee: Apple Inc.

    Inventors: Joseph T. DiBene, II, Inder M. Sodhi, Keith Cox, Gerard R. Williams, III

  • Computation engine that operates in matrix and vector modes

    Patent number: 11042373

    Abstract: In an embodiment, a computation engine is configured to perform vector multiplications, producing either vector results or outer product (matrix) results. The instructions provided to the computation engine specify a matrix mode or a vector mode for the instructions. The computation engine performs the specified operation. The computation engine may perform numerous computations in parallel, in an embodiment. In an embodiment, the instructions may also specify an offset with the input memories, providing additional flexibility in the location of operands. More particularly, the computation engine may be configured to perform numerous multiplication operations in parallel and to accumulate results in a result memory, performing multiply-accumulate operations for each matrix/vector element in the targeted locations of the output memory.

    Type: Grant

    Filed: July 14, 2020

    Date of Patent: June 22, 2021

    Assignee: Apple Inc.

    Inventors: Eric Bainville, Jeffry E. Gonion, Ali Sazegari, Gerard R. Williams, III

  • Marking valid return targets

    Patent number: 10867031

    Abstract: Systems, apparatuses, methods, and computer-readable mediums for preventing return oriented programming (ROP) attacks. A compiler may insert landing pads adjacent to valid return targets in an instruction sequence. When a return instruction is executed, the processor may treat the return as suspicious if the target of the return instruction does not have an adjacent landing pad. Additionally, each landing pad may be encoded with a color, and a colored launch pad may be inserted into the instruction stream next to each return instruction. When a return instruction is executed, the processor may determine if the target of the return has a landing pad with the same color as the launch pad of the return instruction. Return-target pairs with color mismatches may be treated as suspicious and the offending process may be killed.

    Type: Grant

    Filed: July 23, 2015

    Date of Patent: December 15, 2020

    Assignee: Apple Inc.

    Inventors: Gregory D. Hughes, Conrado Blasco, Gerard R. Williams, III, Jacques Anthony Vidrine, Jeffry E. Gonion, Timothy R. Paaske, Tristan F. Schaap

  • Reduced power operation using stored capacitor energy

    Patent number: 10845856

    Abstract: In an embodiment, a system may support a “coast mode” in which the power management unit (PMU) that supplies the supply voltage to an integrated circuit is disabled temporarily for certain modes of the integrated circuit. The integrated circuit may continue to operate, consuming the energy stored in capacitance in and/or around the integrated circuit. When coast mode is initiated, a time interval for coasting may be determined. When the time interval expires, the PMU may re-enable the power supply voltage.

    Type: Grant

    Filed: March 21, 2019

    Date of Patent: November 24, 2020

    Assignee: Apple Inc.

    Inventors: Joseph T. DiBene, II, Inder M. Sodhi, Gerard R. Williams, III

  • Computation engine with extract instructions to minimize memory access

    Patent number: 10831488

    Abstract: In an embodiment, a computation engine may offload work from a processor (e.g. a CPU) and efficiently perform computations such as those used in LSTM and other workloads at high performance. In an embodiment, the computation engine may perform computations on input vectors from input memories in the computation engine, and may accumulate results in an output memory within the computation engine. The input memories may be loaded with initial vector data from memory, incurring the memory latency that may be associated with reading the operands. Compute instructions may be performed on the operands, generating results in an output memory. One or more extract instructions may be supported to move data from the output memory to the input memory, permitting additional computation on the data in the output memory without moving the results to main memory.

    Type: Grant

    Filed: August 20, 2018

    Date of Patent: November 10, 2020

    Assignee: Apple Inc.

    Inventors: Eric Bainville, Jeffry E. Gonion, Ali Sazegari, Gerard R. Williams, III, Andrew J. Beaumont-Smith

  • Computation Engine that Operates in Matrix and Vector Modes

    Publication number: 20200348934

    Abstract: In an embodiment, a computation engine is configured to perform vector multiplications, producing either vector results or outer product (matrix) results. The instructions provided to the computation engine specify a matrix mode or a vector mode for the instructions. The computation engine performs the specified operation. The computation engine may perform numerous computations in parallel, in an embodiment. In an embodiment, the instructions may also specify an offset with the input memories, providing additional flexibility in the location of operands. More particularly, the computation engine may be configured to perform numerous multiplication operations in parallel and to accumulate results in a result memory, performing multiply-accumulate operations for each matrix/vector element in the targeted locations of the output memory.

    Type: Application

    Filed: July 14, 2020

    Publication date: November 5, 2020

    Inventors: Eric Bainville, Jeffry E. Gonion, Ali Sazegari, PhD, Gerard R. Williams, III

  • Systems and methods for performing memory compression

    Patent number: 10769065

    Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.

    Type: Grant

    Filed: June 10, 2019

    Date of Patent: September 8, 2020

    Assignee: Apple Inc.

    Inventors: Ali Sazegari, Charles E. Tucker, Jeffry E. Gonion, Gerard R. Williams, III, Chris Cheng-Chieh Lee

  • Computation engine that operates in matrix and vector modes

    Patent number: 10754649

    Abstract: In an embodiment, a computation engine is configured to perform vector multiplications, producing either vector results or outer product (matrix) results. The instructions provided to the computation engine specify a matrix mode or a vector mode for the instructions. The computation engine performs the specified operation. The computation engine may perform numerous computations in parallel, in an embodiment. In an embodiment, the instructions may also specify an offset with the input memories, providing additional flexibility in the location of operands. More particularly, the computation engine may be configured to perform numerous multiplication operations in parallel and to accumulate results in a result memory, performing multiply-accumulate operations for each matrix/vector element in the targeted locations of the output memory.

    Type: Grant

    Filed: July 24, 2018

    Date of Patent: August 25, 2020

    Assignee: Apple Inc.

    Inventors: Eric Bainville, Jeffry E. Gonion, Ali Sazegari, Gerard R. Williams, III

  • Unified prefetch circuit for multi-level caches

    Patent number: 10621100

    Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit for a multi-level cache system. The access patterns that are matched to the access maps may include prefetches for different cache levels. Centralizing the generation of prefetches into one prefetch circuit may provide better observability and controllability of prefetching at various levels of the cache hierarchy, in an embodiment. Prefetches at different levels may be controlled individually based on the accuracy of those prefetches, in an embodiment. Additionally, in an embodiment, access patterns that are longer that a given threshold may have the granularity of the prefetches change so that more data is prefetched and the prefetches occur farther in advance, in some embodiments.

    Type: Grant

    Filed: December 5, 2018

    Date of Patent: April 14, 2020

    Assignee: Apple Inc.

    Inventors: Stephan G. Meier, Tyler J. Huberty, Gerard R. Williams, III, Pradeep Kanapathipillai

  • Computation Engine that Operates in Matrix and Vector Modes

    Publication number: 20200034145

    Abstract: In an embodiment, a computation engine is configured to perform vector multiplications, producing either vector results or outer product (matrix) results. The instructions provided to the computation engine specify a matrix mode or a vector mode for the instructions. The computation engine performs the specified operation. The computation engine may perform numerous computations in parallel, in an embodiment. In an embodiment, the instructions may also specify an offset with the input memories, providing additional flexibility in the location of operands. More particularly, the computation engine may be configured to perform numerous multiplication operations in parallel and to accumulate results in a result memory, performing multiply-accumulate operations for each matrix/vector element in the targeted locations of the output memory.

    Type: Application

    Filed: July 24, 2018

    Publication date: January 30, 2020

    Inventors: Eric Bainville, Jeffry E. Gonion, Ali Sazegari, Gerard R. Williams, III

  • Systems and Methods for Coherent Power Management

    Publication number: 20190346903

    Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

    Type: Application

    Filed: July 23, 2019

    Publication date: November 14, 2019

    Inventors: Joseph T. DiBene, II, Inder M. Sodhi, Keith Cox, Gerard R. Williams, III

  • Load/store dependency predictor optimization for replayed loads

    Patent number: 10437595

    Abstract: Systems, apparatuses, and methods for optimizing a load-store dependency predictor (LSDP). When a younger load instruction is issued before an older store instruction and the younger load is dependent on the older store, the LSDP is trained on this ordering violation. A replay/flush indicator is stored in a corresponding entry in the LSDP to indicate whether the ordering violation resulted in a flush or replay. On subsequent executions, a dependency may be enforced for the load-store pair if a confidence counter is above a threshold, with the threshold varying based on the status of the replay/flush indicator. If a given load matches on multiple entries in the LSDP, and if at least one of the entries has a flush indicator, then the given load may be marked as a multimatch case and forced to wait to issue until all older stores have issued.

    Type: Grant

    Filed: March 15, 2016

    Date of Patent: October 8, 2019

    Assignee: Apple Inc.

    Inventors: Pradeep Kanapathipillai, Stephan G. Meier, Gerard R. Williams, III, Mridul Agarwal, Kulin N. Kothari

  • SYSTEMS AND METHODS FOR PERFORMING MEMORY COMPRESSION

    Publication number: 20190294541

    Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing are described. In various embodiments, a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.

    Type: Application

    Filed: June 10, 2019

    Publication date: September 26, 2019

    Inventors: Ali Sazegari, Charles E. Tucker, Jeffry E. Gonion, Gerard R. Williams, III, Chris Cheng-Chieh Lee

  • Systems and methods for coherent power management

    Patent number: 10423209

    Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

    Type: Grant

    Filed: February 13, 2017

    Date of Patent: September 24, 2019

    Assignee: Apple Inc.

    Inventors: Joseph T. DiBene, II, Inder M. Sodhi, Keith Cox, Gerard R. Williams, III

  • Processor including multiple dissimilar processor cores that implement different portions of instruction set architecture

    Patent number: 10401945

    Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

    Type: Grant

    Filed: March 26, 2018

    Date of Patent: September 3, 2019

    Assignee: Apple Inc.

    Inventors: David J. Williamson, Gerard R. Williams, III, James N. Hardage, Jr., Richard F. Russo

  • Reduced Power Operation Using Stored Capacitor Energy

    Publication number: 20190212796

    Abstract: In an embodiment, a system may support a “coast mode” in which the power management unit (PMU) that supplies the supply voltage to an integrated circuit is disabled temporarily for certain modes of the integrated circuit. The integrated circuit may continue to operate, consuming the energy stored in capacitance in and/or around the integrated circuit. When coast mode is initiated, a time interval for coasting may be determined. When the time interval expires, the PMU may re-enable the power supply voltage.

    Type: Application

    Filed: March 21, 2019

    Publication date: July 11, 2019

    Inventors: Joseph T. DiBene, II, Inder M. Sodhi, Gerard R. Williams, III

  • Systems and methods for performing memory compression

    Patent number: 10331558

    Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing. A compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.

    Type: Grant

    Filed: July 28, 2017

    Date of Patent: June 25, 2019

    Assignee: Apple Inc.

    Inventors: Ali Sazegari, Charles E. Tucker, Jeffry E. Gonion, Gerard R. Williams, III, Chris Cheng-Chieh Lee

  • Processor including multiple dissimilar processor cores

    Patent number: 10289191

    Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, but may have higher minimum voltage at which it operates correctly. Another core may be implemented at a lower maximum performance, but may be optimized for efficiency and may operate correctly at a lower minimum voltage. The processor may support multiple processor states (PStates). Each PState may specify an operating point and may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core.

    Type: Grant

    Filed: January 9, 2018

    Date of Patent: May 14, 2019

    Assignee: Apple Inc.

    Inventors: David J. Williamson, Gerard R. Williams, III

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